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00033 #ifndef _RTEMS_SCORE_CPU_H
00034 #define _RTEMS_SCORE_CPU_H
00035
00036 #ifdef __cplusplus
00037 extern "C" {
00038 #endif
00039
00040 #include <rtems/score/no_cpu.h>
00041 #ifndef ASM
00042 #include <rtems/score/types.h>
00043 #endif
00044
00045
00046
00068 #define CPU_INLINE_ENABLE_DISPATCH FALSE
00069
00091 #define CPU_UNROLL_ENQUEUE_PRIORITY TRUE
00092
00120 #define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
00121
00133 #define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
00134
00153 #define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE
00154
00167 #define CPU_ALLOCATE_INTERRUPT_STACK TRUE
00168
00178 #define CPU_ISR_PASSES_FRAME_POINTER 0
00179
00215 #if ( NO_CPU_HAS_FPU == 1 )
00216 #define CPU_HARDWARE_FP TRUE
00217 #else
00218 #define CPU_HARDWARE_FP FALSE
00219 #endif
00220 #define CPU_SOFTWARE_FP FALSE
00221
00246 #define CPU_ALL_TASKS_ARE_FP TRUE
00247
00263 #define CPU_IDLE_TASK_IS_FP FALSE
00264
00294 #define CPU_USE_DEFERRED_FP_SWITCH TRUE
00295
00320 #define CPU_PROVIDES_IDLE_THREAD_BODY TRUE
00321
00333 #define CPU_STACK_GROWS_UP TRUE
00334
00358 #define CPU_STRUCTURE_ALIGNMENT
00359
00380 #define CPU_BIG_ENDIAN TRUE
00381
00396 #define CPU_LITTLE_ENDIAN FALSE
00397
00408 #define CPU_MODES_INTERRUPT_MASK 0x00000001
00409
00410
00411
00412
00413
00414
00415
00416
00417
00418
00419
00468 typedef struct {
00472 uint32_t some_integer_register;
00476 uint32_t some_system_register;
00477
00481 uint32_t stack_pointer;
00482 } Context_Control;
00483
00493 #define _CPU_Context_Get_SP( _context ) \
00494 (_context)->stack_pointer
00495
00501 typedef struct {
00503 double some_float_register;
00504 } Context_Control_fp;
00505
00512 typedef struct {
00517 uint32_t special_interrupt_register;
00518 } CPU_Interrupt_frame;
00519
00530 SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context;
00531
00556 SCORE_EXTERN void *_CPU_Interrupt_stack_low;
00557
00563 SCORE_EXTERN void *_CPU_Interrupt_stack_high;
00564
00579 SCORE_EXTERN void (*_CPU_Thread_dispatch_pointer)();
00580
00581
00582
00583
00584
00585
00586
00587
00588
00589
00590
00602 #define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
00603
00613 #define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
00614
00624 #define CPU_INTERRUPT_NUMBER_OF_VECTORS 32
00625
00630 #define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
00631
00637 #define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
00638
00648 #define CPU_STACK_MINIMUM_SIZE (1024*4)
00649
00658 #define CPU_ALIGNMENT 8
00659
00683 #define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT
00684
00701 #define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT
00702
00716 #define CPU_STACK_ALIGNMENT 0
00717
00718
00719
00720
00721
00730 #define _CPU_Initialize_vectors()
00731
00743 #define _CPU_ISR_Disable( _isr_cookie ) \
00744 { \
00745 (_isr_cookie) = 0; \
00746 }
00747
00760 #define _CPU_ISR_Enable( _isr_cookie ) \
00761 { \
00762 }
00763
00777 #define _CPU_ISR_Flash( _isr_cookie ) \
00778 { \
00779 }
00780
00798 #define _CPU_ISR_Set_level( new_level ) \
00799 { \
00800 }
00801
00813 uint32_t _CPU_ISR_Get_level( void );
00814
00815
00816
00817
00818
00850 #define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
00851 _isr, _entry_point, _is_fp ) \
00852 { \
00853 }
00854
00870 #define _CPU_Context_Restart_self( _the_context ) \
00871 _CPU_Context_restore( (_the_context) );
00872
00895 #define _CPU_Context_Fp_start( _base, _offset ) \
00896 ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
00897
00916 #define _CPU_Context_Initialize_fp( _destination ) \
00917 { \
00918 *(*(_destination)) = _CPU_Null_fp_context; \
00919 }
00920
00921
00922
00923
00924
00934 #define _CPU_Fatal_halt( _error ) \
00935 { \
00936 }
00937
00938
00939
00940
00941
00954 #define CPU_USE_GENERIC_BITFIELD_CODE TRUE
00955
00965 #define CPU_USE_GENERIC_BITFIELD_DATA TRUE
00966
01032 #if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
01033 #define _CPU_Bitfield_Find_first_bit( _value, _output ) \
01034 { \
01035 (_output) = 0; \
01036 }
01037 #endif
01038
01039
01040
01050 #if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
01051
01052 #define _CPU_Priority_Mask( _bit_number ) \
01053 ( 1 << (_bit_number) )
01054
01055 #endif
01056
01070 #if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
01071
01072 #define _CPU_Priority_bits_index( _priority ) \
01073 (_priority)
01074
01075 #endif
01076
01077
01078
01079
01080
01090 void _CPU_Initialize(
01091 void (*thread_dispatch)
01092 );
01093
01107 void _CPU_ISR_install_raw_handler(
01108 uint32_t vector,
01109 proc_ptr new_handler,
01110 proc_ptr *old_handler
01111 );
01112
01125 void _CPU_ISR_install_vector(
01126 uint32_t vector,
01127 proc_ptr new_handler,
01128 proc_ptr *old_handler
01129 );
01130
01142 void _CPU_Install_interrupt_stack( void );
01143
01154 void *_CPU_Thread_Idle_body( uint32_t );
01155
01167 void _CPU_Context_switch(
01168 Context_Control *run,
01169 Context_Control *heir
01170 );
01171
01185 void _CPU_Context_restore(
01186 Context_Control *new_context
01187 );
01188
01203 void _CPU_Context_save_fp(
01204 Context_Control_fp **fp_context_ptr
01205 );
01206
01221 void _CPU_Context_restore_fp(
01222 Context_Control_fp **fp_context_ptr
01223 );
01224
01253 static inline uint32_t CPU_swap_u32(
01254 uint32_t value
01255 )
01256 {
01257 uint32_t byte1, byte2, byte3, byte4, swapped;
01258
01259 byte4 = (value >> 24) & 0xff;
01260 byte3 = (value >> 16) & 0xff;
01261 byte2 = (value >> 8) & 0xff;
01262 byte1 = value & 0xff;
01263
01264 swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
01265 return swapped;
01266 }
01267
01275 #define CPU_swap_u16( value ) \
01276 (((value&0xff) << 8) | ((value >> 8)&0xff))
01277
01278 #ifdef __cplusplus
01279 }
01280 #endif
01281
01282 #endif