Processor Dependent Interrupt Management

Defines
#define	CPU_MODES_INTERRUPT_MASK   0x00000001
#define	CPU_INTERRUPT_NUMBER_OF_VECTORS   32
#define	CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER   (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
#define	CPU_PROVIDES_ISR_IS_IN_PROGRESS   FALSE
#define	_CPU_Initialize_vectors()
#define	_CPU_ISR_Disable(_isr_cookie)
#define	_CPU_ISR_Enable(_isr_cookie)
#define	_CPU_ISR_Flash(_isr_cookie)
#define	_CPU_ISR_Set_level(new_level)
Functions
uint32_t	_CPU_ISR_Get_level (void)
void	_CPU_ISR_install_raw_handler (uint32_t vector, proc_ptr new_handler, proc_ptr *old_handler)
void	_CPU_ISR_install_vector (uint32_t vector, proc_ptr new_handler, proc_ptr *old_handler)
void	_CPU_Install_interrupt_stack (void)
Variables
SCORE_EXTERN void *	_CPU_Interrupt_stack_low
SCORE_EXTERN void *	_CPU_Interrupt_stack_high
SCORE_EXTERN void(*	_CPU_Thread_dispatch_pointer )()

---

Detailed Description

On some CPUs, RTEMS supports a software managed interrupt stack. This stack is allocated by the Interrupt Manager and the switch is performed in _ISR_Handler. These variables contain pointers to the lowest and highest addresses in the chunk of memory allocated for the interrupt stack. Since it is unknown whether the stack grows up or down (in general), this give the CPU dependent code the option of picking the version it wants to use.

Note:

These two variables are required if the macro CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.

Port Specific Information:

XXX document implementation including references if appropriate

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Define Documentation

 

#define _CPU_Initialize_vectors

(

)

Support routine to initialize the RTEMS vector table after it is allocated.

Port Specific Information:

XXX document implementation including references if appropriate

#define _CPU_ISR_Disable

(

_isr_cookie

)

Value:

{ \
    (_isr_cookie) = 0;   /* do something to prevent warnings */ \
  }

Disable all interrupts for an RTEMS critical section. The previous level is returned in _isr_cookie.

Parameters:

[out]

_isr_cookie

will contain the previous level cookie

Port Specific Information:

XXX document implementation including references if appropriate

#define _CPU_ISR_Enable

(

_isr_cookie

)

Value:

{ \
  }

Enable interrupts to the previous level (returned by _CPU_ISR_Disable). This indicates the end of an RTEMS critical section. The parameter _isr_cookie is not modified.

Parameters:

[in]

_isr_cookie

contain the previous level cookie

Port Specific Information:

XXX document implementation including references if appropriate

#define _CPU_ISR_Flash

(

_isr_cookie

)

Value:

{ \
  }

This temporarily restores the interrupt to _isr_cookie before immediately disabling them again. This is used to divide long RTEMS critical sections into two or more parts. The parameter _isr_cookie is not modified.

Parameters:

[in]

_isr_cookie

contain the previous level cookie

Port Specific Information:

XXX document implementation including references if appropriate

#define _CPU_ISR_Set_level

(

new_level

)

Value:

{ \
  }

This routine and _CPU_ISR_Get_level Map the interrupt level in task mode onto the hardware that the CPU actually provides. Currently, interrupt levels which do not map onto the CPU in a generic fashion are undefined. Someday, it would be nice if these were "mapped" by the application via a callout. For example, m68k has 8 levels 0 - 7, levels 8 - 255 would be available for bsp/application specific meaning. This could be used to manage a programmable interrupt controller via the rtems_task_mode directive.

Port Specific Information:

XXX document implementation including references if appropriate

#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER   (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)

This defines the highest interrupt vector number for this port.

Referenced by _ISR_Is_vector_number_valid().

#define CPU_INTERRUPT_NUMBER_OF_VECTORS   32

This defines the number of entries in the _ISR_Vector_table managed by RTEMS.

Port Specific Information:

XXX document implementation including references if appropriate

#define CPU_MODES_INTERRUPT_MASK   0x00000001

The following defines the number of bits actually used in the interrupt field of the task mode. How those bits map to the CPU interrupt levels is defined by the routine _CPU_ISR_Set_level.

Port Specific Information:

XXX document implementation including references if appropriate

#define CPU_PROVIDES_ISR_IS_IN_PROGRESS   FALSE

This is defined if the port has a special way to report the ISR nesting level. Most ports maintain the variable _ISR_Nest_level.

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Function Documentation

void _CPU_Install_interrupt_stack

(

void

)

This routine installs the hardware interrupt stack pointer.

Note:

It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK is TRUE.

Port Specific Information:

XXX document implementation including references if appropriate

uint32_t _CPU_ISR_Get_level

(

void

)

Return the current interrupt disable level for this task in the format used by the interrupt level portion of the task mode.

Note:

This routine usually must be implemented as a subroutine.

Port Specific Information:

XXX document implementation including references if appropriate

void _CPU_ISR_install_raw_handler	(	uint32_t	vector,
		proc_ptr	new_handler,
		proc_ptr *	old_handler
	)

This routine installs a "raw" interrupt handler directly into the processor's vector table.

Parameters:

[in]	vector	is the vector number
[in]	new_handler	is the raw ISR handler to install
[in]	old_handler	is the previously installed ISR Handler

Port Specific Information:

XXX document implementation including references if appropriate

void _CPU_ISR_install_vector	(	uint32_t	vector,
		proc_ptr	new_handler,
		proc_ptr *	old_handler
	)

This routine installs an interrupt vector.

Parameters:

[in]	vector	is the vector number
[in]	new_handler	is the RTEMS ISR handler to install
[in]	old_handler	is the previously installed ISR Handler

Port Specific Information:

XXX document implementation including references if appropriate

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Variable Documentation

SCORE_EXTERN void* _CPU_Interrupt_stack_high

This variable points to the lowest physical address of the interrupt stack.

SCORE_EXTERN void* _CPU_Interrupt_stack_low

This variable points to the lowest physical address of the interrupt stack.

SCORE_EXTERN void(* _CPU_Thread_dispatch_pointer)()

With some compilation systems, it is difficult if not impossible to call a high-level language routine from assembly language. This is especially true of commercial Ada compilers and name mangling C++ ones. This variable can be optionally defined by the CPU porter and contains the address of the routine _Thread_Dispatch. This can make it easier to invoke that routine at the end of the interrupt sequence (if a dispatch is necessary).

Port Specific Information:

XXX document implementation including references if appropriate