binutils-2.9.1.0.25 + rtems-patches is broken

[valette at crf.canon.fr (VALETTE Eric)]

>>>>> "Tony" == Tony R Ambardar <tonya at ece.ubc.ca> writes:

Tony> I believe I posted about this before, but it can't hurt to point it out
Tony> again. This code fragment doesn't work as expected. The "i8259s_cache"
Tony> variable is in the BSS, and the BSS will just be zeroed after this code
Tony> executes in start.S. The solution is to move the instruction "movw
Tony> $0xFFFB, SYM(i8259s_cache)" to a point after the BSS is zeroed. That area
Tony> runs in 32-bit protected mode, so it should also fix the other problem
Tony> you're seeing. 

Why not initialize directly the variable in irq.c and remove the line
in  ldseg.S???

BTW : I fixed another bug in irq.c...

  ------------------------------------- patch ------------
*** irq.c       Tue Aug  3 09:41:58 1999
--- irq.c.new   Tue Aug  3 09:41:11 1999
***************
*** 8,14 ****
   *  found in found in the file LICENSE in this distribution or at
   *  http://www.OARcorp.com/rtems/license.html.
   *
!  *  $Id: irq.c,v 1.2 1999/07/29 15:52:26 valette Exp $
   */
  
  
--- 8,14 ----
   *  found in found in the file LICENSE in this distribution or at
   *  http://www.OARcorp.com/rtems/license.html.
   *
!  *  $Id: irq.c,v 1.1.1.1 1999/06/10 09:17:37 valette Exp $
   */
  
  
***************
*** 53,59 ****
   * while upper bits are interrupt on the slave PIC.
   * This cache is initialized in ldseg.s
   */
! rtems_i8259_masks i8259s_cache;
  
  /*-------------------------------------------------------------------------+
  |         Function:  BSP_irq_disable_at_i8259s
--- 53,59 ----
   * while upper bits are interrupt on the slave PIC.
   * This cache is initialized in ldseg.s
   */
! rtems_i8259_masks i8259s_cache = 0xffbf;
  
  /*-------------------------------------------------------------------------+
  |         Function:  BSP_irq_disable_at_i8259s
***************
*** 83,89 ****
    }
    else
    {
!     outport_byte(PIC_SLAVE_IMR_IO_PORT, ((i8259s_cache & 0xff00) >> 8));
    }
    _CPU_ISR_Enable (level);
  
--- 83,89 ----
    }
    else
    {
!     outport_byte(PIC_SLAVE_IMR_IO_PORT, ((i8259s_cache & 0xff00) > 8));
    }
    _CPU_ISR_Enable (level);
  
***************
*** 118,124 ****
    }
    else
    {
!     outport_byte(PIC_SLAVE_IMR_IO_PORT, ((i8259s_cache & 0xff00) >> 8));
    }
    _CPU_ISR_Enable (level);
  
--- 118,124 ----
    }
    else
    {
!     outport_byte(PIC_SLAVE_IMR_IO_PORT, ((i8259s_cache & 0xff00) > 8));
    }
    _CPU_ISR_Enable (level);

 *** ldsegs.S    Tue Aug  3 09:46:00 1999
--- ldsegs.S.new        Thu Jul 15 17:02:15 1999
***************
*** 139,144 ****
--- 139,146 ----
        outb    al, $0x21               /* is cascaded                      */
        call    SYM(delay)
  
+       movw    $0xFFFB, SYM(i8259s_cache) /* set up same values in cache */
+ 
        jmp     SYM (_establish_stack)  # return to the bsp entry code
  
  /*-------------------------------------------------------------------------+
 
  ------------------- end patch -----------------------

-- 
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  /  `                   	Eric Valette
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