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inline assembly problem in psim BSP
- Date: Thu, 11 Feb 1999 09:19:01 -0500
- From: jskulpin at eng01.gdds.com (Jay Kulpinski)
- Subject: inline assembly problem in psim BSP
In trying to run the timing tests on MPC604, I discovered a problem
with inline assembly code borrowed from the PowerPC psim BSP.
I haven't tried to run the timing tests under psim, but I'd guess
it would be a problem there, too.
-------------- next part --------------
*** ./rtems-4.0.0/c/src/lib/libbsp/powerpc/psim/include/bsp.h.orig Wed Apr 15 16:50:22 1998
--- ./rtems-4.0.0/c/src/lib/libbsp/powerpc/psim/include/bsp.h Mon Feb 8 15:52:05 1999
***************
*** 72,94 ****
#define Cause_tm27_intr() \
do { \
unsigned32 _clicks = 1; \
! asm volatile( "mtdec %0" : "=r" ((_clicks)) : "r" ((_clicks)) ); \
} while (0)
#define Clear_tm27_intr() \
do { \
unsigned32 _clicks = 0xffffffff; \
! asm volatile( "mtdec %0" : "=r" ((_clicks)) : "r" ((_clicks)) ); \
} while (0)
#define Lower_tm27_intr() \
do { \
unsigned32 _msr = 0; \
_ISR_Set_level( 0 ); \
! asm volatile( "mfmsr %0 ;" : "=r" (_msr) : "r" (_msr) ); \
_msr |= 0x8002; \
! asm volatile( "mtmsr %0 ;" : "=r" (_msr) : "r" (_msr) ); \
} while (0)
/* Constants */
--- 72,94 ----
#define Cause_tm27_intr() \
do { \
unsigned32 _clicks = 1; \
! asm volatile( "mtdec %0" : : "r" ((_clicks)) ); \
} while (0)
#define Clear_tm27_intr() \
do { \
unsigned32 _clicks = 0xffffffff; \
! asm volatile( "mtdec %0" : : "r" ((_clicks)) ); \
} while (0)
#define Lower_tm27_intr() \
do { \
unsigned32 _msr = 0; \
_ISR_Set_level( 0 ); \
! asm volatile( "mfmsr %0 ;" : "=r" (_msr) : ); \
_msr |= 0x8002; \
! asm volatile( "mtmsr %0 ;" : : "r" (_msr) ); \
} while (0)
/* Constants */