Light on PPC interrupt management requested

[leonp at plris.com (Pollak Leon)]

At 10:45 09/02/99 +0100, you wrote:
>No. Not at all. On Intel one very efficient way to handles the
>saving of floting point registers is as follow :
>       - give the folating point registers to one thread,
>       - on context switch, register the last thread that used
>       the FPU and disable it,
>       - If another thread starts using the FPU, you get an exception.
>       You then save the FPU registers and give the CPU to this new thread.
>       No more exception will occur for this thread

	What HW mechanism supports this?

	As I saw this in RTEMS, there is special flag in TCB which monitors task
FP usage and forces FP context switch if necessary. Isn't it good enough?


Leon Pollak
leonp at plris.com