Light on PPC interrupt management requested

[td at imd.m.ISAR.de (Thomas Doerfler)]

Hi joel, Hi Eric...

here are just some hints from me... 
> 
> eric> is this also valid for 8xx

The 8xx cores have a full 32 bit implementation of the PPC 
architecture, with the following basic restrictions:
- no FPU
- other type of MMU

So the features Eric mentioned are completely true for the MPC8xx 
aswell.
Most of it is true aswell for the PPC4xx from IBM. But these chips 
have additional "features" like a second set of SRRs (SRR2/3) for 
"critical" interrupts...
:->>

> :-(

> 
> >> 5) Is there ways to defer saving of floating point registers until
> >> the first floating point instruction (like on Intel),
> 
> Groumph... Well the question was slightly different although your answer
> is already very important to know. The question is : is there a way
> to make the processor generates an exception whenever someone tries to
> use FP so that we can save FP registers at this point rather than
> on context switch, interrupts...

Well I guess, one way would be to disable the "FP" bit in the machine 
state register everytime a task switch occures. In that case, any FP 
isntruction will trap into the "floating point unavailable" 
exception. There you could switch FP registers and enable the "FP" 
bit "on demand".

Another general question:

I am using the PPC support of RTEMS, and now I am a bit concerned. 
What exactly do you want to modify? Will you feed these modifications 
back to RTEMS? I don't like the idea of having a totally different 
PowerPC support in a future RTEMS release... So I would really like 
to check rather early, whether your modifications are transparent for 
the existing BSPs, like helas403 ;-))))

I guess that the PPC support in RTEMS is not optimal, but it works 
quite well...

Bye,
	Thomas.

--------------------------------------------
IMD Ingenieurbuero fuer Microcomputertechnik
Thomas Doerfler           Herbststrasse 8
D-82178 Puchheim          Germany
email:    td at imd.m.isar.de