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Light on PPC interrupt management requested
- Date: Tue, 9 Feb 1999 13:47:41 +0100 (CET)
- From: valette at crf.canon.fr (VALETTE Eric)
- Subject: Light on PPC interrupt management requested
>>>>> "Thomas" == Thomas Doerfler <td at imd.m.ISAR.de> writes:
Thomas> The 8xx cores have a full 32 bit implementation of the PPC
Thomas> architecture, with the following basic restrictions:
Thomas> - no FPU
Thomas> - other type of MMU
Does it have BATS???
Thomas> So the features Eric mentioned are completely true for the MPC8xx
Thanks for the answer.
Thomas> Well I guess, one way would be to disable the "FP" bit in the machine
Thomas> state register everytime a task switch occures. In that case, any FP
Thomas> isntruction will trap into the "floating point unavailable"
Thomas> exception. There you could switch FP registers and enable the "FP"
Thomas> bit "on demand".
OK that's perfect...
Thomas> I am using the PPC support of RTEMS, and now I am a bit concerned.
Thomas> What exactly do you want to modify?
Probably interrupt mangement PATH as well as FPU management if I have
Thomas>Will you feed these modifications back to RTEMS?
Thomas>I don't like the idea of having a totally different
Thomas> PowerPC support in a future RTEMS release... So I would really like
Thomas> to check rather early, whether your modifications are transparent for
Thomas> the existing BSPs, like helas403 ;-))))
Thomas> I guess that the PPC support in RTEMS is not optimal, but it works
Thomas> quite well...
Well the code I have seen could be largely improved without API modification.
(saving less registers on interrupt entry does not impact the API for
example). I would also like to provide the same kind of Interrupt mangement
API that I have already implemented on Intel as having a single interrupt line
does not give any interrupt pioritiation and the usual set_vector API
does not help...
(see libbsp/i386/shared/irq/irq.h for more details).
/ ` Eric Valette
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