Forseen performance problems with libchip (and other BIG PBS)

[valette at crf.canon.fr (VALETTE Eric)]

>>>>> "Jennifer" == Jennifer Averett <jennifer.averett at OARcorp.com> writes:

Jennifer> I don't completely agree with your differences.  Consider the decrementer
Jennifer> exception used for tick.  You will also have another common exception if
Jennifer> floating-point unavailable exception is used to recover/store floating point
Jennifer> registers as is being discussed.

Ok about the frequency but the fact that they are CPU dependent and not BSP
dependent is still valid...

Eric> First define the exceptions :
Eric> PPC_EXC_xxx (E.g system check, machine check, DSI, ISI, SC, ...)
Eric> and define the API for setting the vectors at the right place.

Jennifer> I don't want to lose the fact that there is a last interrupt called
Jennifer> ..._LAST.  This is important because there is a large variation on the
Jennifer> number of cpu defined exceptions based upon the individual chip (603e vs
Jennifer> 604...).  This allows board support packages to support more than one
Jennifer> revision of the same basic hardware.

You still mix interrupt number and exception number... Tssss
Yet there is a last exeption that is processor dependent as well
as other (power save , termal, ...)

Jennifer> Will a libchip driver be able to work on both a processor that maps the chip
Jennifer> IRQ directly to a cpu interrupt and a processor that maps the chip IRQ to a
Jennifer> external exception, using your implementation?


Yes.

Have a nice week-end,

--eric