mips64orion _CPU_ISR_Set_level

[dank at icube.com (Daniel Kelley)]

I found a small buglet in the mips64orion _CPU_ISR_Set_level; the original was
wiping out the level argument, and then comparing the current interrupt
level with some random value of v0. See patch below.

On a related note, is there a good way for the BSP to override the
interrupt handling (or other CPU components) in exec/score/cpu in the same way that
a BSP can selectively override code in libcpu? I would like to use the interrupt
strategy that I already use for the R4650, but would like to avoid patching non-BSP
sources.



--- old/rtems-4.0.0/c/src/exec/score/cpu/mips64orion/cpu_asm.S	Tue Feb 17 15:44:18 1998
+++ new/rtems-4.0.0/c/src/exec/score/cpu/mips64orion/cpu_asm.S	Tue May 18 07:57:28 1999
@@ -153,12 +153,12 @@
 
 FRAME(_CPU_ISR_Set_level,sp,0,ra)
 	nop
-	mfc0 a0,C0_SR
+	mfc0 v0,C0_SR
 	nop
-	andi a0,SR_EXL 
-	beqz a0,_CPU_ISR_Set_1		/* normalize a0 */
+	andi v0,SR_EXL 
+	beqz v0,_CPU_ISR_Set_1		/* normalize v0 */
 	nop
-	li a0,1         
+	li v0,1         
 _CPU_ISR_Set_1:
 	beq v0,a0,_CPU_ISR_Set_exit	/* if (current_level != new_level ) */
 	nop

--
Daniel Kelley
Senior Member Technical Staff
I-Cube, Inc.                            408-341-1888 x165 (voice)
2605 S. Winchester Blvd.                408-341-1899      (fax)
Campbell, CA 95008 USA