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- Date: Tue, 18 May 1999 12:15:17 -0500 (CDT)
- From: joel at OARcorp.com (joel at OARcorp.com)
- Subject: mips64orion _CPU_ISR_Set_level
On Tue, 18 May 1999, Daniel Kelley wrote:
> I found a small buglet in the mips64orion _CPU_ISR_Set_level; the original was
> wiping out the level argument, and then comparing the current interrupt
> level with some random value of v0. See patch below.
Thanks and merged.
> On a related note, is there a good way for the BSP to override the
> interrupt handling (or other CPU components) in exec/score/cpu in the
> same way that a BSP can selectively override code in libcpu? I would
> like to use the interrupt strategy that I already use for the R4650,
> but would like to avoid patching non-BSP sources.
Take a look at what the i386 now does. Eric Valette has been a strong
proponent of a different organization that allows BSPs to have more
control over the interrupt setup. If this looks like what you need, then
we need to talk. :)
Joel Sherrill, Ph.D. Director of Research & Development
joel at OARcorp.com On-Line Applications Research
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