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- Date: Wed, 19 May 1999 07:54:56 -0700 (PDT)
- From: dank at icube.com (Daniel Kelley)
- Subject: mips64orion _CPU_ISR_Set_level
> From joel at oarcorp.com Tue May 18 10:52:12 1999
> Take a look at what the i386 now does. Eric Valette has been a strong
> proponent of a different organization that allows BSPs to have more
> control over the interrupt setup. If this looks like what you need, then
> we need to talk. :)
Yes, the i386 organization is a lot closer to what I am looking for, as far
as interrupts go.
I am still somewhat confused about _CPU_ISR_Set_level and how important is it
to support interrupt levels for the mips architecture. I see some architectures
support multiple levels if the CPU allows an easy way to do so, otherwise it
just enables and disables interrupts. I could certainly go either way, but I'm
just not sure what the "best" way to go is, knowing that there is no one best way.
So, we need to talk?
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