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- Date: Thu, 20 May 1999 14:03:04 +0200 (CEST)
- From: valette at crf.canon.fr (VALETTE Eric)
- Subject: mips64orion _CPU_ISR_Set_level
>>>>> "Daniel" == Daniel Kelley <dank at icube.com> writes:
>> From joel at oarcorp.com Tue May 18 10:52:12 1999
>> Take a look at what the i386 now does. Eric Valette has been a strong
>> proponent of a different organization that allows BSPs to have more
>> control over the interrupt setup. If this looks like what you need, then
>> we need to talk. :)
Daniel> Yes, the i386 organization is a lot closer to what I am looking for, as far
Daniel> as interrupts go.
I hope to propose something similar for PPC somewhere next week or the week after...
Daniel> I am still somewhat confused about _CPU_ISR_Set_level and how important is it
Daniel> to support interrupt levels for the mips architecture. I see some architectures
Daniel> support multiple levels if the CPU allows an easy way to do so, otherwise it
Daniel> just enables and disables interrupts. I could certainly go either way, but I'm
Daniel> just not sure what the "best" way to go is, knowing that there is no one best way.
I do not know the MIPS but I do know for 68k. I would say that, on some 68k
implementation (BSP like mvme147 for ex) external hardware can be programmed to set
the level at which an interrupt will occur. The processor mask the interrupt up
to that level. So if you use only the processor features, you have only
seven level. If you want/need to have more, then either you must dynamically
lower some interrupt priorities (if there are some that are imposed by hardware
and you dislike the predefined level), or access the exernal harware and use bit
mask to temporarilly disable an interrupt sources or both...