mips64orion _CPU_ISR_Set_level

[dank at icube.com (Daniel Kelley)]

> From joel at oarcorp.com  Wed May 19 10:58:22 1999
> 
> What do you think will be required to get the mips port into a similar
> organization.  
>

in lib/libcpu/mips64orion:

    make a cpu directory "cpu"

    use the following mips cpu API:

        int mips_get_interrupt_level(void)
        int mips_set_interrupt_level(int level)
        void mips_enable_interrupts(int level)
        int  mips_disable_interrupts(void)
        void mips_break(void)
        void mips_initialize_exceptions(void)

     code substantially from exec/score/cpu/mips64orion/cpu_asm.S

     modify Makefile.in to add cpu

     modify clock/ckinit.c to reflect new names for enable_int and
         disable_int

changes to lib/libbsp/mips64orion/p4000:

    modify wrapup/Makefile.in to add cpu to CPU_PIECES

changes to exec/score/cpu/mips64orion/cpu.h:

    change CPU_MODES_INTERRUPT_MASK from '1' to '7'

    Question: is it a problem if the mask is wider than the
              number of interrupt levels? Should it be wider than
              three bits?

    convert _CPU_ISR_Set_level to a macro
    convert _CPU_ISR_Get_level to a macro

    rename disable_int to mips_disable_int
    rename  enable_int to mips_enable_int
    remove comment about changing name



> 
> Eric Valette did this to the i386 and is in the process of doing the same
> thing to the PowerPC.  He has an API definition to go along with this now.  
> How to move this architecture onto the mips is the question.
> 
The API above was gleaned from the existing i386. 

Question for Eric: do you have a "formal" API definition somewhere?

--
Daniel Kelley
Senior Member Technical Staff
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