ISR Latency in Hitachi SH1

[joel.sherrill at OARcorp.com (Joel Sherrill)]

Ralf Corsepius wrote:
> 
> Silverio Diquigiovanni wrote:
> 
> > In WEB I've found this information for all supported CPU except for SH.
> 
> Just for the record:
> 
> The results of the timing testsuite are not available for the SH, because
> we couldn't run most of the tests on our SH-boards due to lack of memory,
> when we were porting RTEMS to the SH1 (256K RAM).

I know I have made progress in cutting down size requirements since 4.0
but I do recall users running all but tm21 on 68000 boards with only 
256K memory.  tm21 allocates 100 each of tasks and a handful of other 
objects to time name->ID services.

Do you recall if none of them would fit or if it was just a subset?

Was it with POSIX enabled or disabled?  Enabling POSIX certainly
causes the minimum to grow in 4.0.

[And I know... that was a while ago. :)]

> --
> Ralf Corsepius
> Forschungsinstitut fuer Anwendungsorientierte Wissensverarbeitung (FAW)
> Helmholtzstr. 16, 89081 Ulm, Germany     Tel: +49/731/501-8690
> mailto:corsepiu at faw.uni-ulm.de           FAX: +49/731/501-999
> http://www.faw.uni-ulm.de

-- 
Joel Sherrill, Ph.D.             Director of Research & Development
joel at OARcorp.com                 On-Line Applications Research
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