BSP for MIPS32 4KC

[mikeci at acm.org (mikeci at acm.org)]

> Ivica,
>
> I am about to start a BSP for the AMD Au1500 which is MIPS32
> and I wonder if you have any specific details on the context
> and interrupt handling changes.  If not, what makes you feel this
> will be the case?
>
> Thanks,
> Michael
>
Michael,

Take look in $RTEMS_HOME/cpukit/score/cpu/mips. There you have cpu.c and
cpu_asm.S. Edit cpu_asm.S and search for function _ISR_Handler. You will
see that this function returns with:

	j         k1
	rfe
        NOP

       .set    reorder
ENDFRAME(_ISR_Handler)

This is incorrect for MIP32. rfe instruction is reserved for R3000 and not
for MIP32.

This is just one small example. All the files in this dierctory should be
updated to support MIP32.


Regards,

Ivica