Possible Missing Memory Barrier on powerpc platform

[strauman at slac.stanford.edu (Till Straumann)]

jennifer at oarcorp.com wrote:
> I am having some strange problems on a powerpc platform and started
> looking at sorce to validate that the Memory Barrier was around all
> portions of inline asm that should contain it.  I have only started
> looking at this but have a question on the file
> c/src/lib/libcpu/powerpc/shared/src/cache.c.  Shouldn't there be a be a
> barrier around the macros for PPC_Get_HID0 and PPC_Set_HID0.
>
> Thanks
> Jennifer Averett
>   
Hard to come up with a quick answer. There are two
'isync' instructions around Set_HID0 and one 'isync'
following 'Get_HID0'.

I suspect that the 'isync' following 'Get_HID0' is unnecessary.

The exact synchronization requirements for 'Set_HID0'
however depend on what bits you modify. Note that HID0,
is implementation specific (different for different CPUs).
In particular, if you are messing with the caches then careful
study of the manual and good understanding is necessary.

Why don't you describe your problem in a little bit more
detail?

-- Till