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Caches on G2 PowerPC/network problem
- Date: Sun, 14 Dec 2008 19:21:16 +0100
- From: Thomas.Doerfler at imd-systems.de (Thomas Doerfler (nt))
- Subject: Caches on G2 PowerPC/network problem
1. Where do you find the hint, that dcbi is forbidden? It is priviledge,
but should be available e.g. on a PPC603e.
2. No matter how you use dcbi or dcbf, you will ALWAYS get problems,
when a cache line contains a data buffer and additional other data
(another buffer or variables).
3.) The MPC82xx family has a "global" bit to control DMA accesses. When
you activate this feature, the DMA will activate the "GLOBAL" line of
the 603 sstem bus, whenever a DMA access occurs. The "GLOBAL" signal
will activate the cache snoop logic and the cache will intervene if it
holds a cache line for the DMA access address visible on the system bus.
- If the cache contains an unmodified copy of the external memory area,
it will invalidate it in the cache
- If the cache contains modified data for that memory area, it will
abort the current DMA access, push the modified data back to external
memory and then allow the DMA access to rerun.
Using the "GLOBAL" attribute therefore will ensure coherency between DMA
and CPU accesses in most practical situations.
Leon Pollak schrieb:
> Gurus in PPC and networking, please, help!
> G2 manual states that usage of dcbi instruction (cache invalidate) is
> forbidden. And they suggest to use dcbf (cache flush) instead.
> This raises the following possible problem.
> Consider the network driver which is going to receive some buffer at address
> X. For this, when the DMA reported that data has arrived, the driver should
> execute FLUSH instruction as they recommend.
> But flush, before invalidating, will check if the corresponding cache line was
> not updated. And if yes, it will flush cache content back to the memory!
> This means, that if one 32byte (CACHE_ALIGNMENT) cache line contains data from
> 2 buffers, the arrived data will be spoiled.
> I do not understand how to solve this, except by guarantying that each buffer
> returned by MGETHDR(...) and MCLGET(...) is cache aligned.
> And how to do this, in turn?
> Many thanks ahead for a help.
IMD Ingenieurbuero fuer Microcomputertechnik
Thomas Doerfler Herbststrasse 8
D-82178 Puchheim Germany
email: Thomas.Doerfler at imd-systems.de
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