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- Date: Mon, 22 Dec 2008 18:49:09 -0600
- From: joel.sherrill at OARcorp.com (Joel Sherrill)
- Subject: Cache Manager
Sebastian Huber wrote:
> is the Cache Manager optional or mandatory for a architecture/BSP?
I would hope that it was a mandatory part but was not an original
part of RTEMS and has not been ported to all architectures.
> I want to change pool allocation in the LibBlock to use cache aligned buffers.
> This is important for boards with no cache coherency support and DMA.
What would this require from the cache manager?
It would be better to assume the support is there and fix it
on architectures where it isn't. This might encourage people.
> Have a nice day!
Joel Sherrill, Ph.D. Director of Research & Development
joel.sherrill at OARcorp.com On-Line Applications Research
Ask me about RTEMS: a free RTOS Huntsville AL 35805
Support Available (256) 722-9985
- Cache Manager
- From: sebastian.huber at embedded-brains.de (Sebastian Huber)