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RTEMS CPU Kit with SuperCore
4.10.99.0
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SPARC basic context. More...
#include <cpu.h>
Data Fields | |
| double | g0_g1 |
| Using a double g0_g1 will put everything in this structure on a double word boundary which allows us to use double word loads and stores safely in the context switch. | |
| uint32_t | g2 |
| This will contain the contents of the g2 register. | |
| uint32_t | g3 |
| This will contain the contents of the g3 register. | |
| uint32_t | g4 |
| This will contain the contents of the g4 register. | |
| uint32_t | g5 |
| This will contain the contents of the g5 register. | |
| uint32_t | g6 |
| This will contain the contents of the g6 register. | |
| uint32_t | g7 |
| This will contain the contents of the g7 register. | |
| uint32_t | l0 |
| This will contain the contents of the l0 register. | |
| uint32_t | l1 |
| This will contain the contents of the l1 register. | |
| uint32_t | l2 |
| This will contain the contents of the l2 register. | |
| uint32_t | l3 |
| This will contain the contents of the l3 register. | |
| uint32_t | l4 |
| This will contain the contents of the l4 register. | |
| uint32_t | l5 |
| This will contain the contents of the l5 registeer. | |
| uint32_t | l6 |
| This will contain the contents of the l6 register. | |
| uint32_t | l7 |
| This will contain the contents of the l7 register. | |
| uint32_t | i0 |
| This will contain the contents of the i0 register. | |
| uint32_t | i1 |
| This will contain the contents of the i1 register. | |
| uint32_t | i2 |
| This will contain the contents of the i2 register. | |
| uint32_t | i3 |
| This will contain the contents of the i3 register. | |
| uint32_t | i4 |
| This will contain the contents of the i4 register. | |
| uint32_t | i5 |
| This will contain the contents of the i5 register. | |
| uint32_t | i6_fp |
| This will contain the contents of the i6 (e.g. | |
| uint32_t | i7 |
| This will contain the contents of the i7 register. | |
| uint32_t | o0 |
| This will contain the contents of the o0 register. | |
| uint32_t | o1 |
| This will contain the contents of the o1 register. | |
| uint32_t | o2 |
| This will contain the contents of the o2 register. | |
| uint32_t | o3 |
| This will contain the contents of the o3 register. | |
| uint32_t | o4 |
| This will contain the contents of the o4 register. | |
| uint32_t | o5 |
| This will contain the contents of the o5 register. | |
| uint32_t | o6_sp |
| This will contain the contents of the o6 (e.g. | |
| uint32_t | o7 |
| This will contain the contents of the o7 register. | |
| uint32_t | psr |
| This will contain the contents of the processor status register. | |
| uint32_t | isr_dispatch_disable |
| This field is used to prevent heavy nesting of calls to _Thread_Dispatch on an interrupted task's stack. | |
SPARC basic context.
This structure defines the basic integer and processor state context for the SPARC architecture.
| uint32_t Context_Control::g2 |
This will contain the contents of the g2 register.
| uint32_t Context_Control::g3 |
This will contain the contents of the g3 register.
| uint32_t Context_Control::g4 |
This will contain the contents of the g4 register.
| uint32_t Context_Control::g5 |
This will contain the contents of the g5 register.
| uint32_t Context_Control::g6 |
This will contain the contents of the g6 register.
| uint32_t Context_Control::g7 |
This will contain the contents of the g7 register.
| uint32_t Context_Control::i0 |
This will contain the contents of the i0 register.
| uint32_t Context_Control::i1 |
This will contain the contents of the i1 register.
| uint32_t Context_Control::i2 |
This will contain the contents of the i2 register.
| uint32_t Context_Control::i3 |
This will contain the contents of the i3 register.
| uint32_t Context_Control::i4 |
This will contain the contents of the i4 register.
| uint32_t Context_Control::i5 |
This will contain the contents of the i5 register.
| uint32_t Context_Control::i6_fp |
This will contain the contents of the i6 (e.g.
frame pointer) register.
| uint32_t Context_Control::i7 |
This will contain the contents of the i7 register.
This field is used to prevent heavy nesting of calls to _Thread_Dispatch on an interrupted task's stack.
This is problematic on the slower SPARC CPU models at high interrupt rates.
| uint32_t Context_Control::l0 |
This will contain the contents of the l0 register.
| uint32_t Context_Control::l1 |
This will contain the contents of the l1 register.
| uint32_t Context_Control::l2 |
This will contain the contents of the l2 register.
| uint32_t Context_Control::l3 |
This will contain the contents of the l3 register.
| uint32_t Context_Control::l4 |
This will contain the contents of the l4 register.
| uint32_t Context_Control::l5 |
This will contain the contents of the l5 registeer.
| uint32_t Context_Control::l6 |
This will contain the contents of the l6 register.
| uint32_t Context_Control::l7 |
This will contain the contents of the l7 register.
| uint32_t Context_Control::o0 |
This will contain the contents of the o0 register.
| uint32_t Context_Control::o1 |
This will contain the contents of the o1 register.
| uint32_t Context_Control::o2 |
This will contain the contents of the o2 register.
| uint32_t Context_Control::o3 |
This will contain the contents of the o3 register.
| uint32_t Context_Control::o4 |
This will contain the contents of the o4 register.
| uint32_t Context_Control::o5 |
This will contain the contents of the o5 register.
| uint32_t Context_Control::o6_sp |
This will contain the contents of the o6 (e.g.
frame pointer) register.
| uint32_t Context_Control::o7 |
This will contain the contents of the o7 register.
| uint32_t Context_Control::psr |
This will contain the contents of the processor status register.
1.7.5