This quote from the ITRON specification needs to be thought about:
"When an interrupt is invoked, the interrupt handler defined with this system call is started directly by the interrupt processing mechanism of the CPU hardware. Accordingly, code at the beginning and end of an interrupt handler must save and restore any registers used by the interrupt handler."
Based on another comment, in the ret_int description, I think this means
that RTEMS will not support the TA_ASM style of interrupt handlers --
only the TA_HLNG style.
When TA_HLNG is specified, a high-level language environment setting program (a high-level language support routine) is called before branching to the inthdr address. The least significant bit (LSB) of the system attribute bits is used for this specification.
Specification allows special "interrupt-only" versions of system
calls named i???_??? (i.e. sig_sem and isig_sem). This does not seem
to be something that would be implemented with RTEMS. We could provide
macros mapping them onto the default versions if this is an issue.
How this operates versus the behavior of a true TRON chip is
up for discussion.
ret_wup is questionable in only high-level language ISRs.
dis_int and ena_int refer to a specific interrupt number. These
may require hooking back out to the BSP.
for chg_iXX and reg_iXX, the XX should be replaced with something
that is meaningful on a particular CPU.