This is i386.info, produced by makeinfo version 4.3 from i386.texi. INFO-DIR-SECTION RTEMS Target Supplements START-INFO-DIR-ENTRY * RTEMS Intel i386 Applications Supplement: (i386). END-INFO-DIR-ENTRY  File: i386.info, Node: Preface, Next: CPU Model Dependent Features, Prev: Top, Up: Top Preface ******* The Real Time Executive for Multiprocessor Systems (RTEMS) is designed to be portable across multiple processor architectures. However, the nature of real-time systems makes it essential that the application designer understand certain processor dependent implementation details. These processor dependencies include calling convention, board support package issues, interrupt processing, exact RTEMS memory requirements, performance data, header files, and the assembly language interface to the executive. For information on the i386 processor, refer to the following documents: * `386 Programmer's Reference Manual, Intel, Order No. 230985-002'. * `386 Microprocessor Hardware Reference Manual, Intel, Order No. 231732-003'. * `80386 System Software Writer's Guide, Intel, Order No. 231499-001'. * `80387 Programmer's Reference Manual, Intel, Order No. 231917-001'. It is highly recommended that the i386 RTEMS application developer obtain and become familiar with Intel's 386 Programmer's Reference Manual.  File: i386.info, Node: CPU Model Dependent Features, Next: CPU Model Dependent Features Introduction, Prev: Preface, Up: Top CPU Model Dependent Features **************************** * Menu: * CPU Model Dependent Features Introduction:: * CPU Model Dependent Features CPU Model Name:: * CPU Model Dependent Features bswap Instruction:: * CPU Model Dependent Features Floating Point Unit::  File: i386.info, Node: CPU Model Dependent Features Introduction, Next: CPU Model Dependent Features CPU Model Name, Prev: CPU Model Dependent Features, Up: CPU Model Dependent Features Introduction ============ Microprocessors are generally classified into families with a variety of CPU models or implementations within that family. Within a processor family, there is a high level of binary compatibility. This family may be based on either an architectural specification or on maintaining compatibility with a popular processor. Recent microprocessor families such as the SPARC or PA-RISC are based on an architectural specification which is independent or any particular CPU model or implementation. Older families such as the M68xxx and the iX86 evolved as the manufacturer strived to produce higher performance processor models which maintained binary compatibility with older models. RTEMS takes advantage of the similarity of the various models within a CPU family. Although the models do vary in significant ways, the high level of compatibility makes it possible to share the bulk of the CPU dependent executive code across the entire family. Each processor family supported by RTEMS has a list of features which vary between CPU models within a family. For example, the most common model dependent feature regardless of CPU family is the presence or absence of a floating point unit or coprocessor. When defining the list of features present on a particular CPU model, one simply notes that floating point hardware is or is not present and defines a single constant appropriately. Conditional compilation is utilized to include the appropriate source code for this CPU model's feature set. It is important to note that this means that RTEMS is thus compiled using the appropriate feature set and compilation flags optimal for this CPU model used. The alternative would be to generate a binary which would execute on all family members using only the features which were always present. This chapter presents the set of features which vary across i386 implementations and are of importance to RTEMS. The set of CPU model feature macros are defined in the file c/src/exec/score/cpu/i386/i386.h based upon the particular CPU model defined on the compilation command line.  File: i386.info, Node: CPU Model Dependent Features CPU Model Name, Next: CPU Model Dependent Features bswap Instruction, Prev: CPU Model Dependent Features Introduction, Up: CPU Model Dependent Features CPU Model Name ============== The macro CPU_MODEL_NAME is a string which designates the name of this CPU model. For example, for the Intel i386 without an i387 coprocessor, this macro is set to the string "i386 with i387".  File: i386.info, Node: CPU Model Dependent Features bswap Instruction, Next: CPU Model Dependent Features Floating Point Unit, Prev: CPU Model Dependent Features CPU Model Name, Up: CPU Model Dependent Features bswap Instruction ================= The macro I386_HAS_BSWAP is set to 1 to indicate that this CPU model has the `bswap' instruction which endian swaps a thirty-two bit quantity. This instruction appears to be present in all CPU models i486's and above.  File: i386.info, Node: CPU Model Dependent Features Floating Point Unit, Next: Calling Conventions, Prev: CPU Model Dependent Features bswap Instruction, Up: CPU Model Dependent Features Floating Point Unit =================== The macro I386_HAS_FPU is set to 1 to indicate that this CPU model has a hardware floating point unit and 0 otherwise. The hardware floating point may be on-chip (as in the case of an i486DX or Pentium) or as a coprocessor (as in the case of an i386/i387 combination).  File: i386.info, Node: Calling Conventions, Next: Calling Conventions Introduction, Prev: CPU Model Dependent Features Floating Point Unit, Up: Top Calling Conventions ******************* * Menu: * Calling Conventions Introduction:: * Calling Conventions Processor Background:: * Calling Conventions Calling Mechanism:: * Calling Conventions Register Usage:: * Calling Conventions Parameter Passing:: * Calling Conventions User-Provided Routines::  File: i386.info, Node: Calling Conventions Introduction, Next: Calling Conventions Processor Background, Prev: Calling Conventions, Up: Calling Conventions Introduction ============ Each high-level language compiler generates subroutine entry and exit code based upon a set of rules known as the compiler's calling convention. These rules address the following issues: * register preservation and usage * parameter passing * call and return mechanism A compiler's calling convention is of importance when interfacing to subroutines written in another language either assembly or high-level. Even when the high-level language and target processor are the same, different compilers may use different calling conventions. As a result, calling conventions are both processor and compiler dependent.  File: i386.info, Node: Calling Conventions Processor Background, Next: Calling Conventions Calling Mechanism, Prev: Calling Conventions Introduction, Up: Calling Conventions Processor Background ==================== The i386 architecture supports a simple yet effective call and return mechanism. A subroutine is invoked via the call (call) instruction. This instruction pushes the return address on the stack. The return from subroutine (ret) instruction pops the return address off the current stack and transfers control to that instruction. It is is important to note that the i386 call and return mechanism does not automatically save or restore any registers. It is the responsibility of the high-level language compiler to define the register preservation and usage convention.  File: i386.info, Node: Calling Conventions Calling Mechanism, Next: Calling Conventions Register Usage, Prev: Calling Conventions Processor Background, Up: Calling Conventions Calling Mechanism ================= All RTEMS directives are invoked using a call instruction and return to the user application via the ret instruction.  File: i386.info, Node: Calling Conventions Register Usage, Next: Calling Conventions Parameter Passing, Prev: Calling Conventions Calling Mechanism, Up: Calling Conventions Register Usage ============== As discussed above, the call instruction does not automatically save any registers. RTEMS uses the registers EAX, ECX, and EDX as scratch registers. These registers are not preserved by RTEMS directives therefore, the contents of these registers should not be assumed upon return from any RTEMS directive.  File: i386.info, Node: Calling Conventions Parameter Passing, Next: Calling Conventions User-Provided Routines, Prev: Calling Conventions Register Usage, Up: Calling Conventions Parameter Passing ================= RTEMS assumes that arguments are placed on the current stack before the directive is invoked via the call instruction. The first argument is assumed to be closest to the return address on the stack. This means that the first argument of the C calling sequence is pushed last. The following pseudo-code illustrates the typical sequence used to call a RTEMS directive with three (3) arguments: push third argument push second argument push first argument invoke directive remove arguments from the stack The arguments to RTEMS are typically pushed onto the stack using a push instruction. These arguments must be removed from the stack after control is returned to the caller. This removal is typically accomplished by adding the size of the argument list in bytes to the stack pointer.  File: i386.info, Node: Calling Conventions User-Provided Routines, Next: Memory Model, Prev: Calling Conventions Parameter Passing, Up: Calling Conventions User-Provided Routines ====================== All user-provided routines invoked by RTEMS, such as user extensions, device drivers, and MPCI routines, must also adhere to these calling conventions.  File: i386.info, Node: Memory Model, Next: Memory Model Introduction, Prev: Calling Conventions User-Provided Routines, Up: Top Memory Model ************ * Menu: * Memory Model Introduction:: * Memory Model Flat Memory Model::  File: i386.info, Node: Memory Model Introduction, Next: Memory Model Flat Memory Model, Prev: Memory Model, Up: Memory Model Introduction ============ A processor may support any combination of memory models ranging from pure physical addressing to complex demand paged virtual memory systems. RTEMS supports a flat memory model which ranges contiguously over the processor's allowable address space. RTEMS does not support segmentation or virtual memory of any kind. The appropriate memory model for RTEMS provided by the targeted processor and related characteristics of that model are described in this chapter.  File: i386.info, Node: Memory Model Flat Memory Model, Next: Interrupt Processing, Prev: Memory Model Introduction, Up: Memory Model Flat Memory Model ================= RTEMS supports the i386 protected mode, flat memory model with paging disabled. In this mode, the i386 automatically converts every address from a logical to a physical address each time it is used. The i386 uses information provided in the segment registers and the Global Descriptor Table to convert these addresses. RTEMS assumes the existence of the following segments: * a single code segment at protection level (0) which contains all application and executive code. * a single data segment at protection level zero (0) which contains all application and executive data. The i386 segment registers and associated selectors must be initialized when the initialize_executive directive is invoked. RTEMS treats the segment registers as system registers and does not modify or context switch them. This i386 memory model supports a flat 32-bit address space with addresses ranging from 0x00000000 to 0xFFFFFFFF (4 gigabytes). Each address is represented by a 32-bit value and is byte addressable. The address may be used to reference a single byte, half-word (2-bytes), or word (4 bytes). RTEMS does not require that logical addresses map directly to physical addresses, although it is desirable in many applications to do so. If logical and physical addresses are not the same, then an additional selector will be required so RTEMS can access the Interrupt Descriptor Table to install interrupt service routines. The selector number of this segment is provided to RTEMS in the CPU Dependent Information Table. By not requiring that logical addresses map directly to physical addresses, the memory space of an RTEMS application can be separated from that of a ROM monitor. For example, on the Force Computers CPU386, the ROM monitor loads application programs into a logical address space where logical address 0x00000000 corresponds to physical address 0x0002000. On this board, RTEMS and the application use virtual addresses which do not map to physical addresses. RTEMS assumes that the DS and ES registers contain the selector for the single data segment when a directive is invoked. This assumption is especially important when developing interrupt service routines.  File: i386.info, Node: Interrupt Processing, Next: Interrupt Processing Introduction, Prev: Memory Model Flat Memory Model, Up: Top Interrupt Processing ******************** * Menu: * Interrupt Processing Introduction:: * Interrupt Processing Vectoring of Interrupt Handler:: * Interrupt Processing Interrupt Stack Frame:: * Interrupt Processing Interrupt Levels:: * Interrupt Processing Disabling of Interrupts by RTEMS:: * Interrupt Processing Interrupt Stack::  File: i386.info, Node: Interrupt Processing Introduction, Next: Interrupt Processing Vectoring of Interrupt Handler, Prev: Interrupt Processing, Up: Interrupt Processing Introduction ============ Different types of processors respond to the occurrence of an interrupt in their own unique fashion. In addition, each processor type provides a control mechanism to allow the proper handling of an interrupt. The processor dependent response to the interrupt modifies the execution state and results in the modification of the execution stream. This modification usually requires that an interrupt handler utilize the provided control mechanisms to return to the normal processing stream. Although RTEMS hides many of the processor dependent details of interrupt processing, it is important to understand how the RTEMS interrupt manager is mapped onto the processor's unique architecture. Discussed in this chapter are the the processor's response and control mechanisms as they pertain to RTEMS.  File: i386.info, Node: Interrupt Processing Vectoring of Interrupt Handler, Next: Interrupt Processing Interrupt Stack Frame, Prev: Interrupt Processing Introduction, Up: Interrupt Processing Vectoring of Interrupt Handler ============================== Although the i386 supports multiple privilege levels, RTEMS and all user software executes at privilege level 0. This decision was made by the RTEMS designers to enhance compatibility with processors which do not provide sophisticated protection facilities like those of the i386. This decision greatly simplifies the discussion of i386 processing, as one need only consider interrupts without privilege transitions. Upon receipt of an interrupt the i386 automatically performs the following actions: * pushes the EFLAGS register * pushes the far address of the interrupted instruction * vectors to the interrupt service routine (ISR). A nested interrupt is processed similarly by the i386.  File: i386.info, Node: Interrupt Processing Interrupt Stack Frame, Next: Interrupt Processing Interrupt Levels, Prev: Interrupt Processing Vectoring of Interrupt Handler, Up: Interrupt Processing Interrupt Stack Frame ===================== The structure of the Interrupt Stack Frame for the i386 which is placed on the interrupt stack by the processor in response to an interrupt is as follows: +----------------------+ | Old EFLAGS Register | ESP+8 +----------+-----------+ | UNUSED | Old CS | ESP+4 +----------+-----------+ | Old EIP | ESP +----------------------+  File: i386.info, Node: Interrupt Processing Interrupt Levels, Next: Interrupt Processing Disabling of Interrupts by RTEMS, Prev: Interrupt Processing Interrupt Stack Frame, Up: Interrupt Processing Interrupt Levels ================ Although RTEMS supports 256 interrupt levels, the i386 only supports two - enabled and disabled. Interrupts are enabled when the interrupt-enable flag (IF) in the extended flags (EFLAGS) is set. Conversely, interrupt processing is inhibited when the IF is cleared. During a non-maskable interrupt, all other interrupts, including other non-maskable ones, are inhibited. RTEMS interrupt levels 0 and 1 such that level zero (0) indicates that interrupts are fully enabled and level one that interrupts are disabled. All other RTEMS interrupt levels are undefined and their behavior is unpredictable.  File: i386.info, Node: Interrupt Processing Disabling of Interrupts by RTEMS, Next: Interrupt Processing Interrupt Stack, Prev: Interrupt Processing Interrupt Levels, Up: Interrupt Processing Disabling of Interrupts by RTEMS ================================ During the execution of directive calls, critical sections of code may be executed. When these sections are encountered, RTEMS disables interrupts before the execution of this section and restores them to the previous level upon completion of the section. RTEMS has been optimized to insure that interrupts are disabled for less than 13.0 microseconds on a 16 Mhz i386 with zero wait states. These numbers will vary based the number of wait states and processor speed present on the target board. [NOTE: The maximum period with interrupts disabled within RTEMS was last calculated for Release 3.1.0.] Non-maskable interrupts (NMI) cannot be disabled, and ISRs which execute at this level MUST NEVER issue RTEMS system calls. If a directive is invoked, unpredictable results may occur due to the inability of RTEMS to protect its critical sections. However, ISRs that make no system calls may safely execute as non-maskable interrupts.  File: i386.info, Node: Interrupt Processing Interrupt Stack, Next: Default Fatal Error Processing, Prev: Interrupt Processing Disabling of Interrupts by RTEMS, Up: Interrupt Processing Interrupt Stack =============== The i386 family does not support a dedicated hardware interrupt stack. On this processor, RTEMS allocates and manages a dedicated interrupt stack. As part of vectoring a non-nested interrupt service routine, RTEMS switches from the stack of the interrupted task to a dedicated interrupt stack. When a non-nested interrupt returns, RTEMS switches back to the stack of the interrupted stack. The current stack pointer is not altered by RTEMS on nested interrupt. Without a dedicated interrupt stack, every task in the system MUST have enough stack space to accommodate the worst case stack usage of that particular task and the interrupt service routines COMBINED. By supporting a dedicated interrupt stack, RTEMS significantly lowers the stack requirements for each task. RTEMS allocates the dedicated interrupt stack from the Workspace Area. The amount of memory allocated for the interrupt stack is determined by the interrupt_stack_size field in the CPU Configuration Table.  File: i386.info, Node: Default Fatal Error Processing, Next: Default Fatal Error Processing Introduction, Prev: Interrupt Processing Interrupt Stack, Up: Top Default Fatal Error Processing ****************************** * Menu: * Default Fatal Error Processing Introduction:: * Default Fatal Error Processing Default Fatal Error Handler Operations::  File: i386.info, Node: Default Fatal Error Processing Introduction, Next: Default Fatal Error Processing Default Fatal Error Handler Operations, Prev: Default Fatal Error Processing, Up: Default Fatal Error Processing Introduction ============ Upon detection of a fatal error by either the application or RTEMS the fatal error manager is invoked. The fatal error manager will invoke the user-supplied fatal error handlers. If no user-supplied handlers are configured, the RTEMS provided default fatal error handler is invoked. If the user-supplied fatal error handlers return to the executive the default fatal error handler is then invoked. This chapter describes the precise operations of the default fatal error handler.  File: i386.info, Node: Default Fatal Error Processing Default Fatal Error Handler Operations, Next: Board Support Packages, Prev: Default Fatal Error Processing Introduction, Up: Default Fatal Error Processing Default Fatal Error Handler Operations ====================================== The default fatal error handler which is invoked by the fatal_error_occurred directive when there is no user handler configured or the user handler returns control to RTEMS. The default fatal error handler disables processor interrupts, places the error code in EAX, and executes a HLT instruction to halt the processor.  File: i386.info, Node: Board Support Packages, Next: Board Support Packages Introduction, Prev: Default Fatal Error Processing Default Fatal Error Handler Operations, Up: Top Board Support Packages ********************** * Menu: * Board Support Packages Introduction:: * Board Support Packages System Reset:: * Board Support Packages Processor Initialization::  File: i386.info, Node: Board Support Packages Introduction, Next: Board Support Packages System Reset, Prev: Board Support Packages, Up: Board Support Packages Introduction ============ An RTEMS Board Support Package (BSP) must be designed to support a particular processor and target board combination. This chapter presents a discussion of i386 specific BSP issues. For more information on developing a BSP, refer to the chapter titled Board Support Packages in the RTEMS Applications User's Guide.  File: i386.info, Node: Board Support Packages System Reset, Next: Board Support Packages Processor Initialization, Prev: Board Support Packages Introduction, Up: Board Support Packages System Reset ============ An RTEMS based application is initiated when the i386 processor is reset. When the i386 is reset, * The EAX register is set to indicate the results of the processor's power-up self test. If the self-test was not executed, the contents of this register are undefined. Otherwise, a non-zero value indicates the processor is faulty and a zero value indicates a successful self-test. * The DX register holds a component identifier and revision level. DH contains 3 to indicate an i386 component and DL contains a unique revision level indicator. * Control register zero (CR0) is set such that the processor is in real mode with paging disabled. Other portions of CR0 are used to indicate the presence of a numeric coprocessor. * All bits in the extended flags register (EFLAG) which are not permanently set are cleared. This inhibits all maskable interrupts. * The Interrupt Descriptor Register (IDTR) is set to point at address zero. * All segment registers are set to zero. * The instruction pointer is set to 0x0000FFF0. The first instruction executed after a reset is actually at 0xFFFFFFF0 because the i386 asserts the upper twelve address until the first intersegment (FAR) JMP or CALL instruction. When a JMP or CALL is executed, the upper twelve address lines are lowered and the processor begins executing in the first megabyte of memory. Typically, an intersegment JMP to the application's initialization code is placed at address 0xFFFFFFF0.  File: i386.info, Node: Board Support Packages Processor Initialization, Next: Processor Dependent Information Table, Prev: Board Support Packages System Reset, Up: Board Support Packages Processor Initialization ======================== This initialization code is responsible for initializing all data structures required by the i386 in protected mode and for actually entering protected mode. The i386 must be placed in protected mode and the segment registers and associated selectors must be initialized before the initialize_executive directive is invoked. The initialization code is responsible for initializing the Global Descriptor Table such that the i386 is in the thirty-two bit flat memory model with paging disabled. In this mode, the i386 automatically converts every address from a logical to a physical address each time it is used. For more information on the memory model used by RTEMS, please refer to the Memory Model chapter in this document. Since the processor is in real mode upon reset, the processor must be switched to protected mode before RTEMS can execute. Before switching to protected mode, at least one descriptor table and two descriptors must be created. Descriptors are needed for a code segment and a data segment. ( This will give you the flat memory model.) The stack can be placed in a normal read/write data segment, so no descriptor for the stack is needed. Before the GDT can be used, the base address and limit must be loaded into the GDTR register using an LGDT instruction. If the hardware allows an NMI to be generated, you need to create the IDT and a gate for the NMI interrupt handler. Before the IDT can be used, the base address and limit for the idt must be loaded into the IDTR register using an LIDT instruction. Protected mode is entered by setting thye PE bit in the CR0 register. Either a LMSW or MOV CR0 instruction may be used to set this bit. Because the processor overlaps the interpretation of several instructions, it is necessary to discard the instructions from the read-ahead cache. A JMP instruction immediately after the LMSW changes the flow and empties the processor if intructions which have been pre-fetched and/or decoded. At this point, the processor is in protected mode and begins to perform protected mode application initialization. If the application requires that the IDTR be some value besides zero, then it should set it to the required value at this point. All tasks share the same i386 IDTR value. Because interrupts are enabled automatically by RTEMS as part of the initialize_executive directive, the IDTR MUST be set properly before this directive is invoked to insure correct interrupt vectoring. If processor caching is to be utilized, then it should be enabled during the reset application initialization code. The reset code which is executed before the call to initialize_executive has the following requirements: For more information regarding the i386s data structures and their contents, refer to Intel's 386 Programmer's Reference Manual.  File: i386.info, Node: Processor Dependent Information Table, Next: Processor Dependent Information Table Introduction, Prev: Board Support Packages Processor Initialization, Up: Top Processor Dependent Information Table ************************************* * Menu: * Processor Dependent Information Table Introduction:: * Processor Dependent Information Table CPU Dependent Information Table::  File: i386.info, Node: Processor Dependent Information Table Introduction, Next: Processor Dependent Information Table CPU Dependent Information Table, Prev: Processor Dependent Information Table, Up: Processor Dependent Information Table Introduction ============ Any highly processor dependent information required to describe a processor to RTEMS is provided in the CPU Dependent Information Table. This table is not required for all processors supported by RTEMS. This chapter describes the contents, if any, for a particular processor type.  File: i386.info, Node: Processor Dependent Information Table CPU Dependent Information Table, Next: Memory Requirements, Prev: Processor Dependent Information Table Introduction, Up: Processor Dependent Information Table CPU Dependent Information Table =============================== The i386 version of the RTEMS CPU Dependent Information Table contains the information required to interface a Board Support Package and RTEMS on the i386. This information is provided to allow RTEMS to interoperate effectively with the BSP. The C structure definition is given here: typedef struct { void (*pretasking_hook)( void ); void (*predriver_hook)( void ); void (*idle_task)( void ); boolean do_zero_of_workspace; unsigned32 idle_task_stack_size; unsigned32 interrupt_stack_size; unsigned32 extra_mpci_receive_server_stack; void * (*stack_allocate_hook)( unsigned32 ); void (*stack_free_hook)( void* ); /* end of fields required on all CPUs */ unsigned32 interrupt_segment; void *interrupt_vector_table; } rtems_cpu_table; `pretasking_hook' is the address of the user provided routine which is invoked once RTEMS APIs are initialized. This routine will be invoked before any system tasks are created. Interrupts are disabled. This field may be NULL to indicate that the hook is not utilized. `predriver_hook' is the address of the user provided routine that is invoked immediately before the the device drivers and MPCI are initialized. RTEMS initialization is complete but interrupts and tasking are disabled. This field may be NULL to indicate that the hook is not utilized. `postdriver_hook' is the address of the user provided routine that is invoked immediately after the the device drivers and MPCI are initialized. RTEMS initialization is complete but interrupts and tasking are disabled. This field may be NULL to indicate that the hook is not utilized. `idle_task' is the address of the optional user provided routine which is used as the system's IDLE task. If this field is not NULL, then the RTEMS default IDLE task is not used. This field may be NULL to indicate that the default IDLE is to be used. `do_zero_of_workspace' indicates whether RTEMS should zero the Workspace as part of its initialization. If set to TRUE, the Workspace is zeroed. Otherwise, it is not. `idle_task_stack_size' is the size of the RTEMS idle task stack in bytes. If this number is less than MINIMUM_STACK_SIZE, then the idle task's stack will be MINIMUM_STACK_SIZE in byte. `interrupt_stack_size' is the size of the RTEMS allocated interrupt stack in bytes. This value must be at least as large as MINIMUM_STACK_SIZE. `extra_mpci_receive_server_stack' is the extra stack space allocated for the RTEMS MPCI receive server task in bytes. The MPCI receive server may invoke nearly all directives and may require extra stack space on some targets. `stack_allocate_hook' is the address of the optional user provided routine which allocates memory for task stacks. If this hook is not NULL, then a stack_free_hook must be provided as well. `stack_free_hook' is the address of the optional user provided routine which frees memory for task stacks. If this hook is not NULL, then a stack_allocate_hook must be provided as well. `interrupt_segment' is the value of the selector which should be placed in a segment register to access the Interrupt Descriptor Table. `interrupt_vector_table' is the base address of the Interrupt Descriptor Table relative to the interrupt_segment. The contents of the i386 Interrupt Descriptor Table are discussed in Intel's i386 User's Manual. Structure definitions for the i386 IDT is provided by including the file rtems.h.  File: i386.info, Node: Memory Requirements, Next: Memory Requirements Introduction, Prev: Processor Dependent Information Table CPU Dependent Information Table, Up: Top Memory Requirements ******************* * Menu: * Memory Requirements Introduction:: * Memory Requirements Data Space Requirements:: * Memory Requirements Minimum and Maximum Code Space Requirements:: * Memory Requirements RTEMS Code Space Worksheet:: * Memory Requirements RTEMS RAM Workspace Worksheet::  File: i386.info, Node: Memory Requirements Introduction, Next: Memory Requirements Data Space Requirements, Prev: Memory Requirements, Up: Memory Requirements Introduction ============ Memory is typically a limited resource in real-time embedded systems, therefore, RTEMS can be configured to utilize the minimum amount of memory while meeting all of the applications requirements. Worksheets are provided which allow the RTEMS application developer to determine the amount of RTEMS code and RAM workspace which is required by the particular configuration. Also provided are the minimum code space, maximum code space, and the constant data space required by RTEMS.  File: i386.info, Node: Memory Requirements Data Space Requirements, Next: Memory Requirements Minimum and Maximum Code Space Requirements, Prev: Memory Requirements Introduction, Up: Memory Requirements Data Space Requirements ======================= RTEMS requires a small amount of memory for its private variables. This data area must be in RAM and is separate from the RTEMS RAM Workspace. The following illustrates the data space required for all configurations of RTEMS: * Data Space: 833  File: i386.info, Node: Memory Requirements Minimum and Maximum Code Space Requirements, Next: Memory Requirements RTEMS Code Space Worksheet, Prev: Memory Requirements Data Space Requirements, Up: Memory Requirements Minimum and Maximum Code Space Requirements =========================================== A maximum configuration of RTEMS includes the core and all managers, including the multiprocessing manager. Conversely, a minimum configuration of RTEMS includes only the core and the following managers: initialization, task, interrupt and fatal error. The following illustrates the code space required by these configurations of RTEMS: * Minimum Configuration: 22,660 * Maximum Configuration: 39,592  File: i386.info, Node: Memory Requirements RTEMS Code Space Worksheet, Next: Memory Requirements RTEMS RAM Workspace Worksheet, Prev: Memory Requirements Minimum and Maximum Code Space Requirements, Up: Memory Requirements RTEMS Code Space Worksheet ========================== The RTEMS Code Space Worksheet is a tool provided to aid the RTEMS application designer to accurately calculate the memory required by the RTEMS run-time environment. RTEMS allows the custom configuration of the executive by optionally excluding managers which are not required by a particular application. This worksheet provides the included and excluded size of each manager in tabular form allowing for the quick calculation of any custom configuration of RTEMS. The RTEMS Code Space Worksheet is below: RTEMS Code Space Worksheet The following is a list of the components of the RTEMS code space. The first number in parentheses is the size when the component is included, while the second number indicates its size when not included. If the second number is "NA", then the component must always be included. * Core (16,948, NA) * Initialization (916, NA) * Task (3,436, NA) * Interrupt (52, NA) * Clock (296, NA) * Timer (1,084, 144) * Semaphore (1,500, 136) * Message (1,596, 224) * Event (1,036, 44) * Signal (396, 44) * Partition (1,052, 104) * Region (1,392, 124) * Dual Ported Memory (664, 104) * I/O (676, 00) * Fatal Error (20, NA) * Rate Monotonic (1,132, 136) * Multiprocessing (6,840, 228)  File: i386.info, Node: Memory Requirements RTEMS RAM Workspace Worksheet, Next: Timing Specification, Prev: Memory Requirements RTEMS Code Space Worksheet, Up: Memory Requirements RTEMS RAM Workspace Worksheet ============================= The RTEMS RAM Workspace Worksheet is a tool provided to aid the RTEMS application designer to accurately calculate the minimum memory block to be reserved for RTEMS use. This worksheet provides equations for calculating the amount of memory required based upon the number of objects configured, whether for single or multiple processor versions of the executive. This information is presented in tabular form, along with the fixed system requirements, allowing for quick calculation of any application defined configuration of RTEMS. The RTEMS RAM Workspace Worksheet is provided below: RTEMS RAM Workspace Worksheet The total RTEMS RAM Workspace required is the sum of the following: * maximum_tasks * 372 * maximum_timers * 68 * maximum_semaphores * 124 * maximum_message_queues * 148 * maximum_regions * 144 * maximum_partitions * 56 * maximum_ports * 36 * maximum_periods * 36 * maximum_extensions * 64 * Floating Point Tasks * 108 * Task Stacks * maximum_nodes * 48 * maximum_global_objects * 20 * maximum_proxies * 124 * Fixed System Requirements of 6,768  File: i386.info, Node: Timing Specification, Next: Timing Specification Introduction, Prev: Memory Requirements RTEMS RAM Workspace Worksheet, Up: Top Timing Specification ******************** * Menu: * Timing Specification Introduction:: * Timing Specification Philosophy:: * Timing Specification Methodology::  File: i386.info, Node: Timing Specification Introduction, Next: Timing Specification Philosophy, Prev: Timing Specification, Up: Timing Specification Introduction ============ This chapter provides information pertaining to the measurement of the performance of RTEMS, the methods of gathering the timing data, and the usefulness of the data. Also discussed are other time critical aspects of RTEMS that affect an applications design and ultimate throughput. These aspects include determinancy, interrupt latency and context switch times.  File: i386.info, Node: Timing Specification Philosophy, Next: Timing Specification Determinancy, Prev: Timing Specification Introduction, Up: Timing Specification Philosophy ========== * Menu: * Timing Specification Determinancy:: * Timing Specification Interrupt Latency:: * Timing Specification Context Switch Time:: * Timing Specification Directive Times:: Benchmarks are commonly used to evaluate the performance of software and hardware. Benchmarks can be an effective tool when comparing systems. Unfortunately, benchmarks can also be manipulated to justify virtually any claim. Benchmarks of real-time executives are difficult to evaluate for a variety of reasons. Executives vary in the robustness of features and options provided. Even when executives compare favorably in functionality, it is quite likely that different methodologies were used to obtain the timing data. Another problem is that some executives provide times for only a small subset of directives, This is typically justified by claiming that these are the only time-critical directives. The performance of some executives is also very sensitive to the number of objects in the system. To obtain any measure of usefulness, the performance information provided for an executive should address each of these issues. When evaluating the performance of a real-time executive, one typically considers the following areas: determinancy, directive times, worst case interrupt latency, and context switch time. Unfortunately, these areas do not have standard measurement methodologies. This allows vendors to manipulate the results such that their product is favorably represented. We have attempted to provide useful and meaningful timing information for RTEMS. To insure the usefulness of our data, the methodology and definitions used to obtain and describe the data are also documented.  File: i386.info, Node: Timing Specification Determinancy, Next: Timing Specification Interrupt Latency, Prev: Timing Specification Philosophy, Up: Timing Specification Philosophy Determinancy ------------ The correctness of data in a real-time system must always be judged by its timeliness. In many real-time systems, obtaining the correct answer does not necessarily solve the problem. For example, in a nuclear reactor it is not enough to determine that the core is overheating. This situation must be detected and acknowledged early enough that corrective action can be taken and a meltdown avoided. Consequently, a system designer must be able to predict the worst-case behavior of the application running under the selected executive. In this light, it is important that a real-time system perform consistently regardless of the number of tasks, semaphores, or other resources allocated. An important design goal of a real-time executive is that all internal algorithms be fixed-cost. Unfortunately, this goal is difficult to completely meet without sacrificing the robustness of the executive's feature set. Many executives use the term deterministic to mean that the execution times of their services can be predicted. However, they often provide formulas to modify execution times based upon the number of objects in the system. This usage is in sharp contrast to the notion of deterministic meaning fixed cost. Almost all RTEMS directives execute in a fixed amount of time regardless of the number of objects present in the system. The primary exception occurs when a task blocks while acquiring a resource and specifies a non-zero timeout interval. Other exceptions are message queue broadcast, obtaining a variable length memory block, object name to ID translation, and deleting a resource upon which tasks are waiting. In addition, the time required to service a clock tick interrupt is based upon the number of timeouts and other "events" which must be processed at that tick. This second group is composed primarily of capabilities which are inherently non-deterministic but are infrequently used in time critical situations. The major exception is that of servicing a clock tick. However, most applications have a very small number of timeouts which expire at exactly the same millisecond (usually none, but occasionally two or three).  File: i386.info, Node: Timing Specification Interrupt Latency, Next: Timing Specification Context Switch Time, Prev: Timing Specification Determinancy, Up: Timing Specification Philosophy Interrupt Latency ----------------- Interrupt latency is the delay between the CPU's receipt of an interrupt request and the execution of the first application-specific instruction in an interrupt service routine. Interrupts are a critical component of most real-time applications and it is critical that they be acted upon as quickly as possible. Knowledge of the worst case interrupt latency of an executive aids the application designer in determining the maximum period of time between the generation of an interrupt and an interrupt handler responding to that interrupt. The interrupt latency of an system is the greater of the executive's and the applications's interrupt latency. If the application disables interrupts longer than the executive, then the application's interrupt latency is the system's worst case interrupt disable period. The worst case interrupt latency for a real-time executive is based upon the following components: * the longest period of time interrupts are disabled by the executive, * the overhead required by the executive at the beginning of each ISR, * the time required for the CPU to vector the interrupt, and * for some microprocessors, the length of the longest instruction. The first component is irrelevant if an interrupt occurs when interrupts are enabled, although it must be included in a worst case analysis. The third and fourth components are particular to a CPU implementation and are not dependent on the executive. The fourth component is ignored by this document because most applications use only a subset of a microprocessor's instruction set. Because of this the longest instruction actually executed is application dependent. The worst case interrupt latency of an executive is typically defined as the sum of components (1) and (2). The second component includes the time necessry for RTEMS to save registers and vector to the user-defined handler. RTEMS includes the third component, the time required for the CPU to vector the interrupt, because it is a required part of any interrupt. Many executives report the maximum interrupt disable period as their interrupt latency and ignore the other components. This results in very low worst-case interrupt latency times which are not indicative of actual application performance. The definition used by RTEMS results in a higher interrupt latency being reported, but accurately reflects the longest delay between the CPU's receipt of an interrupt request and the execution of the first application-specific instruction in an interrupt service routine. The actual interrupt latency times are reported in the Timing Data chapter of this supplement.  File: i386.info, Node: Timing Specification Context Switch Time, Next: Timing Specification Directive Times, Prev: Timing Specification Interrupt Latency, Up: Timing Specification Philosophy Context Switch Time ------------------- An RTEMS context switch is defined as the act of taking the CPU from the currently executing task and giving it to another task. This process involves the following components: * Saving the hardware state of the current task. * Optionally, invoking the TASK_SWITCH user extension. * Restoring the hardware state of the new task. RTEMS defines the hardware state of a task to include the CPU's data registers, address registers, and, optionally, floating point registers. Context switch time is often touted as a performance measure of real-time executives. However, a context switch is performed as part of a directive's actions and should be viewed as such when designing an application. For example, if a task is unable to acquire a semaphore and blocks, a context switch is required to transfer control from the blocking task to a new task. From the application's perspective, the context switch is a direct result of not acquiring the semaphore. In this light, the context switch time is no more relevant than the performance of any other of the executive's subroutines which are not directly accessible by the application. In spite of the inappropriateness of using the context switch time as a performance metric, RTEMS context switch times for floating point and non-floating points tasks are provided for comparison purposes. Of the executives which actually support floating point operations, many do not report context switch times for floating point context switch time. This results in a reported context switch time which is meaningless for an application with floating point tasks. The actual context switch times are reported in the Timing Data chapter of this supplement.  File: i386.info, Node: Timing Specification Directive Times, Next: Timing Specification Methodology, Prev: Timing Specification Context Switch Time, Up: Timing Specification Philosophy Directive Times --------------- Directives are the application's interface to the executive, and as such their execution times are critical in determining the performance of the application. For example, an application using a semaphore to protect a critical data structure should be aware of the time required to acquire and release a semaphore. In addition, the application designer can utilize the directive execution times to evaluate the performance of different synchronization and communication mechanisms. The actual directive execution times are reported in the Timing Data chapter of this supplement.  File: i386.info, Node: Timing Specification Methodology, Next: Timing Specification Software Platform, Prev: Timing Specification Directive Times, Up: Timing Specification Methodology =========== * Menu: * Timing Specification Software Platform:: * Timing Specification Hardware Platform:: * Timing Specification What is measured?:: * Timing Specification What is not measured?:: * Timing Specification Terminology::  File: i386.info, Node: Timing Specification Software Platform, Next: Timing Specification Hardware Platform, Prev: Timing Specification Methodology, Up: Timing Specification Methodology Software Platform ----------------- The RTEMS timing suite is written in C. The overhead of passing arguments to RTEMS by C is not timed. The times reported represent the amount of time from entering to exiting RTEMS. The tests are based upon one of two execution models: (1) single invocation times, and (2) average times of repeated invocations. Single invocation times are provided for directives which cannot easily be invoked multiple times in the same scenario. For example, the times reported for entering and exiting an interrupt service routine are single invocation times. The second model is used for directives which can easily be invoked multiple times in the same scenario. For example, the times reported for semaphore obtain and semaphore release are averages of multiple invocations. At least 100 invocations are used to obtain the average.